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rev. 0 a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? analog devices, inc., 2002 AD7485 1 msps, serial 14-bit sar adc features fast throughput rate: 1 msps wide input bandwidth: 40 mhz excellent dc accuracy performance flexible serial interface low power: 80 mw (full power) and 3 mw (nap mode) standby mode: 2 a max single 5 v supply operation internal 2.5 v reference full-scale overrange indication functional block diagram 2.5 v reference buf t/h av dd a gnd c bias dv dd dgnd refsel refout refin vin 14-bit algorithmic sar nap stby reset convst mclk tfs sco control logic and i/o registers smode AD7485 v drive sdo general description the AD7485 is a 14-bit, high speed, low power, successive- approximation adc. the part features a serial interface with throughput rates up to 1 msps. the part contains a low noise, wide bandwidth track-and-hold that can handle input frequen cies in excess of 40 mhz. the conversion process is a proprietary algorithmic successive- approximation technique. the input signal is sampled and a conversion is initiated on the falling edge of the convst signal. the conversion process is controlled by an external master clock. interfacing is via standard serial signal lines, making the part directly compatible with microcontrollers and dsps. the AD7485 provides excellent ac and dc performance specifi- cations. factory trimming ensures high dc accuracy resulting in very low inl, dnl, offset, and gain errors. the part uses advanced design techniques to achieve very low power dissipation at high throughput rates. power consumption in the normal mode of operation is 80 mw. there are two power- saving modes: a nap mode keeps reference circuitry alive for quick power-up and consumes 3 mw, w hile a standby mode reduces power consumption to a mere 10 w. the AD7485 features an on-board 2.5 v reference, but the part can also accommodate an externally provided 2.5 v reference source. the nominal analog input range is 0 v to 2.5 v. the AD7485 also provides the user with overrange indication via a fifteenth bit. if the analog input range strays outside the 0 v to 2.5 v input range, the fifteenth data bit is set to a logic high. the AD7485 is powered from a 4.75 v to 5.25 v supply. the part also provides a v drive pin that allows the user to set the voltage levels for the digital interface lines. the range for this v drive pin is from 2.7 v to 5.25 v. the part is housed in a 48-lead lqfp package and is specified over a C 40 c to +85 c temperature range.
rev. 0 e2e AD7485especifications 1 parameter specification unit test conditions/comments dynamic performance 2, 3 f in = 500 khz sine wave signal to noise + distortion (sinad) 4 76.5 db min 78 db typ 77 db typ internal reference total harmonic distortion (thd) 4 ? 90 db max ? 95 db typ ? 92 db typ internal reference peak harmonic or spurious noise (sfdr) 4 ? 88 db max intermodulation distortion (imd) 4 second-order terms ? 96 db typ f in1 = 95.053 khz, f in2 = 105.329 khz third-order terms ? 94 db typ aperture delay 10 ns typ full power bandwidth 40 mhz typ @ 3 db 3.5 mhz typ @ 0.1 db dc accuracy resolution 14 bits integral nonlinearity 4 1lsb max 0.5 lsb typ differential nonlinearity 4 0.75 lsb max guaranteed no missed codes to 14 bits 0.25 lsb typ offset error 4 6lsb max 0.036 %fsr max gain error 4 6lsb max 0.036 %fsr max analog input input voltage 0 v min 2.5 v max dc leakage current 1 a max input capacitance 5 35 pf typ reference input/output v refin input voltage 2.5 v 1% for specified performance v refin input dc leakage current 1 a max v refin input capacitance 5 25 pf typ v refin input current 6 220
rev. 0 AD7485 e3e parameter specification unit test conditions/comments power requirements v dd 5v 5% v drive 2.7 v min 5.25 v max i dd normal mode (static) 12 ma max normal mode (operational) 16 ma max nap mode 0.6 ma max standby mode 8 2 a max 0.5 a typ power dissipation normal mode (operational) 80 mw max nap mode 3 mw max standby mode 8 10 w max notes 1 temperature ranges as follows: ? 40 c to +85 c. 2 sinad figures quoted include external analog input circuit noise contribution of approximately 1 db. 3 see typical performance characteristics section for analog input circuits used. 4 see terminology. 5 sample tested @ 25 c to ensure compliance. 6 current drawn from external reference during conversion. 7 i load = 200 a. 8 digital input levels at gnd or v drive . specifications subject to change without notice. parameter symbol min typ max unit master clock frequency f mclk 0.01 25 mhz mclk period t 1 40 100000 ns conversion time t 2 t 1
rev. 0 e4e AD7485 absolute maximum ratings * (t a = 25 c, unless otherwise noted.) v dd to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . ? 0.3 v to +7 v v drive to gnd . . . . . . . . . . . . . . . . . . . . . . . . ? 0.3 v to +7 v analog input voltage to gnd . . . . . . ? 0.3 v to av dd + 0.3 v digital input voltage to gnd . . . . . ? 0.3 v to v drive + 0.3 v refin to gnd . . . . . . . . . . . . . . . . ? 0.3 v to av dd + 0.3 v input current to any pin except supplies . . . . . . . . . 10 ma operating temperature range commercial . . . . . . . . . . . . . . . . . . . . . . . . ? 40 c to +85 c storage temperature range . . . . . . . . . . . . ? 65 c to +150 c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150 c pin configuration 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 39 38 37 43 42 41 40 pin 1 identifier top view (not to scale) smode tfs dgnd dgnd v drive dgnd dgnd av dd c bias a gnd a gnd av dd a gnd vin refout refin refsel a gnd dv dd dgnd dgnd dgnd AD7485 a gnd dgnd a gnd a gnd av dd dv dd dgnd dgnd reset convst sco dgnd dgnd dgnd av dd a gnd a gnd stby nap mclk dgnd dgnd sdo dgnd dgnd dgnd
rev. 0 AD7485 ? pin function descriptions pin no. mnemonic description 1, 5, 13, 46 av dd positive power supply for analog circuitry 2c bias decoupling pin for internal bias voltage. a 1 nf capacitor should be placed between this pin and agnd. 3, 4, 6, 11, 12, agnd power supply ground for analog circuitry 14, 15, 47, 48 7v in analog input. single-ended analog input channel. 8 refout reference output. refout connects to the output of the internal 2.5 v reference buffer. a 470 nf capacitor must be placed between this pin and agnd. 9 refin reference input. a 470 nf capacitor must be placed between this pin and agnd. when using an external voltage reference source, the reference voltage should be applied to this pin. 10 refsel reference decoupling pin. when using the internal reference, a 1 nf capacitor must be connected from this pin to agnd. when using an external reference source, this pin should be connected directly to agnd. 16 stby standby logic input. when this pin is logic high, the device will be placed in standby mode. see the power saving section for further details. 17 nap nap logic input. when this pin is logic high, the device will be placed in a very low power mode. see the power saving section for further details. 18 mclk master clock input. this is the input for the master clock, which controls the conversion cycle. the fre- quency of this clock may be up to 25 mhz. twenty-four clock cycles are required for each conversion. 19, 20, 22 C 28 dgnd ground reference for digital circuitry 30, 31, 33, 34 37 C 39, 43, 44 21 sdo serial data output. the conversion data is latched out on this pin on the rising edge of sco. it should be latched into the receiving serial port of the dsp on the falling edge of sco. the over- range bit is latched out first, then 14 bits of data (msb first) followed by a trailing zero. 29, 45 dv dd positive power supply for digital circuitry 32 v drive logic power supply input. the voltage supplied at this pin determines at what voltage the interface logic of the AD7485 will operate. 35 tfs transmit frame sync input. in serial mode 2, this pin acts as a framing signal for the serial data being clocked out on sdo. a falling edge on tfs brings sdo out of three-state and the data starts to get clocked out on the next rising edge of sco. 36 smode serial mode input. a logic low on this pin selects serial mode 1 and a logic high selects serial mode 2. see the serial interface section for further details. 40 sco serial clock output. this clock is derived from mclk and is used to latch conversion data from the device. see the serial interface section for further details. 41 convst convert start logic input. a conversion is initiated on the falling edge of the convst signal. the input track/hold amplifier goes from track mode to hold mode and the conversion process commences. 42 reset reset logic input. a falling edge on this pin resets the internal state machine and terminates a conversion that may be in progress. holding this pin low keeps the part in a reset state.
rev. 0 e6e AD7485 terminology integral nonlinearity this is the maximum deviation from a straight line passing through the endpoints of the adc transfer function. the end- points of the transfer function are zero scale, a point 1/2 lsb below the first code transition, and full scale, a point 1/2 lsb above the last code transition. differential nonlinearity this is the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. offset error this is the deviation of the first code transition (00 . . . 000) to (00 . . . 001) from the ideal, i.e., agnd + 0.5 lsb. gain error this is the deviation of the last code transition (111 . . . 110) to (111 . . . 111) from the ideal (i.e., v ref ? 1.5 lsb) after the offset error has been adjusted out. track/hold acquisition time track/hold acquisition time is the time required for the output of the track/hold amplifier to reach its final value, within 1/2 lsb, after the end of conversion (the point at which the track/hold returns to track mode). signal to (noise + distortion) ratio this is the measured ratio of signal to (noise + distortion) at the output of the a/d converter. the signal is the rms ampli tude of the fundamental. noise is the sum of all nonfundamental signals up to half the sampling frequency (f s /2), excluding dc. the ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quanti- zation noise. the theoretical signal to (noise + distortion) ratio for an ideal n-bit converter with a sine wave input is given by: signal to noise distortion n db ().. +=+ () 602 176 thus, for a 14-bit converter this is 86.04 db . total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of the harmonics to the fundamental. for the AD7485, it is defined as: thd db log vvvvv v () = ++++ 20 2 2 3 2 4 2 5 2 6 2 1 where v 1 is the rms amplitude of the fundamental and v 2 , v 3 , v 4 , v 5 , and v 6 are the rms amplitudes of the second through sixth harmonics. peak harmonic or spurious noise peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the adc output spectrum (up to f s /2 and excluding dc) to the rms value of the fundamental. normally, the value of this specification is deter- mined by the largest harmonic in the spectrum, but for adcs where the harmonics are buried in the noise floor, it will be a noise peak. intermodulation distortion with inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa nfb where m, n = 0, 1, 2, 3, and so on. intermodulation distortion terms are those for which neither m nor n is equal to zero. for example, the second-order terms include (fa + fb) and (fa ? fb), while the third-order terms include (2fa + fb), (2fa ? fb), (fa + 2fb), and (fa ? 2fb). the AD7485 is tested using the ccif standard where two input frequencies near the top end of the input bandwidth are used. in this case, the second-order terms are usually distanced in frequency from the original sine waves while the third-order terms are usually at a frequency close to the input frequencies. as a result, the second- and third-order terms are specified sepa rately. the calculation of the intermodulation distortion is as per the thd specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in dbs.
rev. 0 t ypical performance characteristicseAD7485 e7e adc code 1.0 0.6 0 dnl e lsb 0.2 e0.2 e0.6 e1.0 4096 8192 12288 16384 0.8 0.4 0 e0.4 e0.8 tpc 1. typical dnl adc code 1.0 0.6 0 inl e lsb 0.2 e0.2 e0.6 e1.0 4096 8192 12288 16384 0.8 0.4 0 e0.4 e0.8 tpc 2. typical inl input frequency e khz 10 sinad e db 75 65 100 1000 10000 80 70 tpc 3. sinad vs. input tone (ad8021 input circuit) input frequency e khz 100 thd e db e60 e100 1000 10000 e40 e80 e90 e70 e50 100 51 10 0 tpc 4. thd vs. input tone for different input resistances frequency e khz 10 psrr e db e20 e60 100 1000 0 e40 e50 e30 e10 e80 e70 100mv p-p sine wave on supply pins tpc 5. psrr without decoupling temperature e c e55 refout e v e0.0004 35 125 0.0004 e0.0008 e0.0012 0 e0.0020 e0.0016 e25 5 65 95 tpc 6. reference error
rev. 0 e8e AD7485 frequency e khz 0 300 100 200 400 500 db e40 0 e60 e80 e20 e120 e100 e140 f in = 10.7khz snr = 78.76db snr + d = 78.70db thd = e97.10db tpc 7. 64k fft plot with 10 khz input tone frequency e khz db e40 0 e60 e80 e20 e120 e100 e140 0 300 100 200 400 500 f in = 507.3khz snr = 78.35db snr + d = 78.33db thd = e100.33db tpc 8. 64k fft plot with 500 khz input tone 220 bias vo ltag e 1 2 3 4 5 6 7 8 ad8021 50 ac signal 220 10pf ev s +v s e + v in 10pf figure 2. analog input circuit used for 500 khz input tone 1 2 3 4 5 6 7 8 ad829 1k 1k 100 ac signal bias vo ltag e 150 220pf ev s +v s e + v in figure 1. analog input circuit used for 10 khz input tone figure 1 shows the analog input circuit used to obtain the data for the fft plot shown in tpc 7. the circuit uses an analog devices ad829 op amp as the input buffer. a bipolar analog signal is applied as shown and biased up with a stable, low noise dc voltage connected to the labeled terminal shown. a 220 pf compensation capacitor is connected between pin 5 of the ad829 and the analog ground plane. the ad829 is supplied with +12 v and ? 12 v supplies. the supply pins are decoupled as close to the device as possible, with both a 0.1 f and 10 f capacitor connected to each pin. in each case, the 0.1 f capacitor should be the closer of the two capacitors to the device. more information on the ad829 is available on the analog devices website. for higher input bandwidth applications, analog devices ? ad8021 op amp (also available as a dual ad8022) is the recommended choice to drive the AD7485. figure 2 shows the analog input circuit used to obtain the data for the fft plot shown in tpc 8. a bipolar analog signal is applied to the terminal shown and biased with a stable, low noise dc voltage connected as shown. a 10 pf compensation capacitor is connected between pin 5 of the ad8021 and the negative supply. as with the previous circuit, the ad8021 is supplied with +12 v and ? 12 v supplies. the supply pins are decoupled as close to the device as possible with both a 0.1 f and 10 f capacitor connected to each pin. in each case, the 0.1 f capacitor should be the closer of the two capaci- tor s to the device. the ad8021 logic reference pin is tied to analog ground and the disable p in is tied to the positive sup- ply as shown. detailed information on the ad8021 is available on the analog devices website.
rev. 0 AD7485 e9e circuit description converter operation the AD7485 is a 14-bit algorithmic successive-approximation analog-to-digital converter based around a capacitive dac. it pro- vides the user with track -and- hold, reference, an a/d converter, and versatile interface logic functions on a single chip. the analog input signal range that the AD7485 can convert is 0 v to 2.5 v. the part requires a 2.5 v reference that can be provided from the part ? s ow n internal reference or an external reference source. figure 3 shows a very simplified schematic of the adc. the control logic, sar, and capacitive dac are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator back to a balanced condition. capacitive dac switches v in v ref sar control logic control inputs output data 14-bit serial comparator figure 3. simplified block diagram conversion is initiated on the AD7485 by pulsing the convst input. on the falling edge of convst , the track/hold goes from track to hold mode and the conversion sequence is started. conversion time for the part is 24 mclk periods. figure 4 shows the adc during conversion. when conversion starts, sw2 will open and sw1 will move to position b causing the comparator to become unbalanced. the adc then runs through its successive approximation routine and brings the comparator back into a balanced condition. when the comparator is rebalanced, the conversion result is available in the sar register. capacitive dac comparator control logic + e sw1 sw2 a gnd v in a b figure 4. adc conversion phase at the end of conversion, track-and-hold returns to tracking mode and the acquisition time begins. the track/ hold acquisi tion time is 70 ns. figure 5 shows the adc during its acquisition phase. sw2 is closed and sw1 is in position a. the comparator is held in a balanced condition and the sampling capacitor acquires the signal on v in . capacitive dac comparator control logic + e sw1 sw2 a gnd v in a b figure 5. adc acquisition phase adc transfer function the output coding of the AD7485 is straight binary. the de signed code transitions occur midway between successive integer lsb values (i.e., 1/2 lsb, 3/2 lsb, and so on). the lsb size is v ref /16384. the nominal transfer characteristic for the AD7485 is shown in figure 6. 000...000 0v adc code analog input 111...111 000...001 000...010 111...110 111...000 011...111 0.5lsb +v ref e1.5lsb 1lsb = v ref /16384 figure 6. transfer characteristic power saving the AD7485 uses advanced design techniques to achieve very low power dissipation at high throughput rates. in addition to this, the AD7485 features two power saving modes, nap mode and standby mode. these modes are selected by bringing either the nap or stby pin to a logic high. when operating the AD7485 with a 25 mhz mclk in normal, fully powered mode, the current consumption is 16 ma during conversion and the quiescent current is 12 ma. operating at a throughput rate of 500 ksps, the conversion time of 960 ns contributes 38.4 mw to the overall power dissipation. ns s v ma mw /. ss v ma mw () () = thus the power dissipated during each cycle is: 38 4 31 2 69 6 ... mw mw mw +=
rev. 0 e10e AD7485 figure 7 shows the AD7485 conversion sequence operating in normal mode. 2 s 960ns 1.04 s read data conversion f inished c onvst tfs figure 7. normal mode power dissipation in nap mode, all the internal circuitry except for the internal reference is powered down. in this mode, the power dissipation of the AD7485 is reduced to 3 mw. when exiting nap mode, a minimum of 300 ns when using an external reference must be waited before initiating a conversion. this is necessary to allow the internal circuitry to settle after power-up and for the track/hold to properly acquire the analog input signal. if the AD7485 is put into nap mode after each conversion, the average power dissipation will be reduced but the throughput rate will be limited by the power-up time. using the AD7485 with a throughput rate of 100 ksps while placing the part in nap mode after each conversion would result in average power dissi- pation as follows: the power-up phase contributes: ns s v ma mw /. ns s v ma mw /. ssv ma mw () () = thus the power dissipated during each cycle is: 18 768 2 622 12 1 .. . . mw mw mw mw ++ + figure 8 shows the AD7485 conversion sequence if putting the part into nap mode after each conversion. 1.26 s 10 s 8.74 s 300ns c onvst nap tfs figure 8. nap mode power dissipation figures 9 and 10 show a typical graphical representation of power versus throughput for the AD7485 when in normal and nap modes, respectively. throughput e ksps 80 76 0 100 power e mw 72 68 64 60 200 400 300 500 600 700 800 900 1000 78 74 70 66 62 figure 9. normal mode, power vs. throughput throughput e ksps 50 40 050 power e mw 30 20 10 0 100 200 150 250 300 350 400 450 500 45 35 25 15 5 figure 10. nap mode, power vs. throughput in standby mode, all the internal circuitry is powered down and the power consumption of the AD7485 is reduced to 10 w. because the internal reference has been powered down, the power-up time necessary before a conversion can be initiated is longer. if using the internal reference of the AD7485, the adc must be brought out of standby mode 500 ms before a conver- sion is initiated. initiating a conversion before the required power-up time has elapsed will result in incorrect conversion data. if an external reference source is used and kept powered up while the AD7485 is in standby mode, the power-up time required w ill be reduced to 80 s.
rev. 0 AD7485 e11e serial interface the AD7485 has two serial interface modes, selected by the state of the smode pin. in both these modes, the mclk pin must be supplied with a clock signal of between 10 khz and 25 mhz. this mclk signal controls the internal conversion process and is also used to derive the sco signal. as the AD7485 uses an algorithmic successive-approximation technique, 24 mclk cycles are required to complete a conversion. due to the error-correcting operation of this adc, all bit trials must be completed before the conversion result is calculated. this results in a single sample delay in the result that is clocked out. in serial mode 1 (figure 13), the convst pin is used to initiate the conversion and also frame the serial data. when convst is brought low, the sdo line is taken out of three- state, the overrange bit will be clocked out on the next rising edge of sco followed by the 14 data bits (msb first) and a trailing zero. convst must remain low for 22 sco pulses to allow all the data to be clocked out and the conversion in progress to be completed. when convst returns to a logic high, the sdo line returns to three-state. tfs should be tied to ground in this mode. in serial mode 2 (figure 14), the convst pin is used to initiate the conversion, but the tfs signal is used to frame the serial data. the convst signal can idle high or low in this mode. idling high, the convst pulsewidth must be between 10 ns and two mclk periods. idling low, the convst pulsewidth must be at least 10 ns. tfs must remain low for a minimum of 22 sco cycles in this mode but can also be tied permanently low. if tfs is tied low, the sdo line will always be driven. the relationship between the mclk and sco signals is shown in figure 15. figure 11 shows a typical connection diagram for the AD7485. in this case, the mclk signal is provided by a 25 mhz crystal oscillator module. it could also be provided by the second serial port of a dsp (e.g., adsp-2189m) if one were available. in figure 11 the v drive pin is tied to dv dd , which results in logic output levels being either 0 v or dv dd . the voltage applied to v drive controls the voltage value of the output logic signals. for example, if dv dd is supplied by a 5 v supply and v drive by a 3 v supply, the logic output levels would be either 0 v or 3 v. this feature allows the AD7485 to interface to 3 v devices while still enabling the a/d to process signals at 5 v supply. the maximum slew rate at the input of the adc should be limited to 500 v/ s while the conversion is taking place. this will prevent corruption of the current conversion. in any multi- plexed application, the channel switching should occur as early as possible after the first mclk period. c/ p reset smode nap stby convst tfs sco sdo c bias refsel refin refout v in AD7485 adm809 v drive dv dd av dd 0.1 f digital supply 4.75ve5.25v 10 f 1nf + 0.1 f 0.1 f + 47 f analog supply 4.75ve5.25v 0v to 2.5v 1nf 0.47 f 0.47 f ad780 2.5v reference 25mhz xo mclk figure 11. typical connection diagram driving the convst t convst s convst t f in ), tim ing jitter ( t j ), and resulting snr is given by the equation below. snr db ft in j j itter () log () = 10 1 2 2 as an example, if the desired snr due to jitter was 100 db with a maximum full-scale analog input frequency of 500 khz, ignor- ing all other noise sources we get an allowable jitter of 3.18 ps on the convst falling edge. for a 14-bit converter (ideal snr = 86.04 db), the allowable jitter will be greater than the figure given above; but due consideration needs to be given to the design of the convst circuitry to achieve 14-bit performance with large analog input frequencies.
rev. 0 e12e AD7485 board layout and grounding to obtain optimum performance from the AD7485, it is recom- mended that a printed circuit board with a minimum of three layers is used. one of these layers, preferably the middle layer, should be as complete a ground plane as possible to give the best shielding. the board should be designed in such a way that the analog and digital circuitry are separated and confined to certain areas of the board. this practice, along with avoiding running digital and analog lines close together, should help to avoid coupling digital noise onto analog lines. the power supply lines to the AD7485 should be approximately 3 mm wide to provide a low impedance path and reduce the effects of glitches on the power supply lines. it is vital that good decoupling is also present. a combination of ferrites and decoupling capacitors should be used as shown in figure 11. the decoupling capacitors should be as close to the supply pins as possible. this is made easier by the use of multilayer boards. the signal traces from the AD7485 pins can be run on the top layer while the decoupling capacitors and ferrites mounted on the bottom layer where the power traces exist. the ground plane between the top and bottom planes provides excellent shielding. figures 12a ? 12e show a sample layout of the board area imme- diately surrounding the AD7485. pin 1 is the bottom left corner of the device. figure 12a shows the top layer where the AD7485 is mounted with vias to the bottom routing layer highlighted. figure 12b shows the bottom layer where the power routing is with the same vias highlighted. figure 12c shows the bottom layer silkscreen where the decoupling components are soldered directly beneath the device. figure 12d shows the silkscreen overlaid on the solder pads for the decoupling components, and figure 12e shows the top and bottom routing layers overlaid. the black area in each figure indicates the ground plane present on the middle layer. figure 12a figure 12b figure 12c figure 12d figure 12e c1-6 : 100 nf, c7 ? 8: 470 nf, c9: 1 nf l1-4: meggit-sigma chip ferrite beads (bmb2a0600rs2)
rev. 0 AD7485 e13e d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 t 7 t 1 t 5 t 3 t 2 t 4 t 11 t 10 t 9 t 8 t 6 c onvst mclk sco sdo figure 13. serial mode 1 (smode = 0) read cycle c onvst mclk sco sdo tfs d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 t 7 t 14 t 15 t 17 t 18 t 16 t 10 t 9 t 6 t 1 t 5 t 2 t 12 t 13 figure 14. serial mode 2 (smode = 1) read cycle mclk sco t 21 t 19 t 20 t 1 t 5 t 6 figure 15. serial clock timing
rev. 0 e14e AD7485 outline dimensions 48-lead plastic quad flatpack [lqfp] 1.4 mm thick (st-48) dimensions shown in millimeters top view (pins down) 1 12 13 25 24 36 37 48 0.27 0.22 0.17 0.50 bsc 7.00 bsc seating plane 1.60 max 0.75 0.60 0.45 view a 7 3.5 0 0.20 0.09 1.45 1.40 1.35 0.15 0.05 0.08 max coplanarity view a rotated 90 ccw pin 1 indicator 9.00 bsc compliant to jedec standards ms-026bbc seating plane
e15e
c02758e0e10/02(0) printed in u.s.a. e16e

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